This patent relates to capacitive transducers, and more particularly to techniques for reducing or eliminating nonlinearities due to spurious capacitances and residual electrostatic forces in capacitive transducers using less circuitry.
Transducers convert a general physical quantity (for example, acceleration, pressure, etc.) to quantities that can be processed by electronic circuits. In particular, capacitive transducers produce a change of capacitance, corresponding to the magnitude of the measured input signal. Readout circuits for capacitive transducers transform the capacitance change produced by the transducer to an electrical signal. In the process, the circuits apply voltage waveforms to the transducer electrodes.
A capacitive accelerometer, a capacitive transducer for measuring acceleration, includes a mechanical sensing element and a readout circuit. FIG. 1 illustrates an exemplary embodiment of a mechanical sensing element 100 of a capacitive accelerometer. In this embodiment, the mechanical sensing element 100 includes a proofmass 102 suspended between a first spring 104 and a second spring 106, a first electrode 110 and a second electrode 112. A proximal end of the mass 102 is coupled to the first spring 104 and a distal end of the mass 102 is coupled to the second spring 106. The first spring 104 has two ends; a first end coupled to the proximal end of the mass 102 and a second end coupled to a substrate. The second spring 106 has two ends; a first end coupled to the distal end of the mass 102 and a second end coupled to the substrate. A common electrode M is coupled to the mass 102 and moves with the mass 102 relative to the substrate. The first and second electrodes 110, 112 are stationary relative to the substrate. In this embodiment a positive reference voltage VS is applied to the first electrode 110 and the negative reference voltage −VS is applied to the second electrode 112. A first variable capacitor C1 is formed between the first electrode 110 and the common electrode M, and a second variable capacitor C2 is formed between the second electrode 112 and the common electrode M.
In this embodiment, when the system is at rest, there is a substantially equal nominal gap g0 between the first electrode 110 and the common electrode M and between the second electrode 112 and the common electrode M, creating substantially equal capacitances in the first variable capacitor C1 and the second variable capacitor C2. An input acceleration moves the mass 102 relative to the substrate which varies the gaps between the electrodes and varies the capacitance of the variable capacitors C1, C2. Acceleration in the direction of arrow 120 deflects the mass 102 a distance Δx that is proportional to the input acceleration. This movement of the mass 102 increases the distance between the first electrode 110 and the common electrode M to g0+Δx, and decreases the distance between the second electrode 112 and the common electrode M to g0−Δx, which changes the capacitance of capacitors C1 and C2. The capacitance C of variable capacitors C1 and C2 can be determined by:
                              C                      1            /            2                          =                                            ɛ              0                        ⁢            A                                              g              0                        ±                          Δ              ⁢                                                          ⁢              x                                                          (        1        )            where ∈0 is dielectric permittivity, A is the area of the capacitive plates (which extend into the paper), g0 is the nominal gap and Δx is the displacement due to the acceleration. The readout circuit determines the value of Δx based on the capacitance change in capacitors C1 and C2.
Accelerometers are often implemented in harsh vibration-ridden environments, for example automotive or industrial environments. In these environments, the accelerometers are typically need good linearity, low drift performance and large full scale range. Self-balanced accelerometers are usually chosen for these applications. Self-balanced accelerometers measure (C1−C2)/(C1+C2).
FIG. 2 is a schematic of an exemplary embodiment of a self-balancing capacitive bridge 200. The switched-capacitor implementation shown in FIG. 2 has the advantage of straightforward DC biasing of the input without the need for a high resistance path, as well as a stable and well-defined transfer function over process and temperature. It also provides a discrete-time output signal, which can be digitized directly by an analog-to-digital converter (ADC). FIG. 2 shows a single-ended embodiment of a self-balancing bridge.
The self-balancing bridge 200 includes a sensor core and a readout or interface circuit. The sensor core 210 represents a capacitive sensor element, for example the sensing element 100 shown in FIG. 1 or one of various other capacitive sensor elements known in the art. The sensor core 210 includes two variable capacitors, C1 and C2, sharing a common node M that is coupled to the output of the sensor core 210. The readout circuit includes a forward path that passes the output of the sensor core 210 through an integrator 222, which provides gain, to the output V0. In this embodiment, the integrator 222 includes an amplifier 224 with an integrating capacitor Ci. The self-balancing bridge 200 also includes a first feedback path 230 and a second feedback path 240 that feedback the output voltage Vo to the sensor core 210. The first feedback path 230 feeds back the output voltage Vo through a first inverting amplifier 232 to a first summing node 234. The first summing node 234 sums the inverted output voltage −V0 and inverted reference voltage −VS, and outputs the resulting voltage −VS−V0 to the first variable sensor capacitor C1. The second feedback path 240 feeds back the output voltage Vo through a second inverting amplifier 242 to a second summing node 244. The second summing node 244 sums the inverted output voltage −V0 and reference voltage VS, and outputs the resulting voltage VS−V0 to the second variable sensor capacitor C2.
The self-balancing bridge 200 tries to equalize the absolute charge on the two sensor capacitors, C1 and C2. Under these conditions the output voltage is proportional to the ratio between the difference and the sum of the measured capacitors:
                              V          o                =                              -                          V              s                                ⁢                                                    C                1                            -                              C                2                                                                    C                1                            +                              C                2                                                                        (        2        )            Measuring the above ratio is of interest for a variety of applications, acceleration sensors being only one particular example.
Equation (2) shows that V0 is proportional to (C1−C2)/(C1+C2), and from Eq. (1) we know that C is proportional to 1/d, where d is the distance between the capacitive plates. Combining these two relationships provides:
                              Vo          ∝                                                    C                1                            -                              C                2                                                                    C                1                            +                              C                2                                                    =                                                                              1                  /                  d                                ⁢                                                                  ⁢                1                            -                                                1                  /                  d                                ⁢                                                                  ⁢                2                                                                                      1                  /                  d                                ⁢                                                                  ⁢                1                            +                                                1                  /                  d                                ⁢                                                                  ⁢                2                                              =                                                                      d                  ⁢                                                                          ⁢                  2                                -                                  d                  ⁢                                                                          ⁢                  1                                                                              d                  ⁢                                                                          ⁢                  2                                +                                  d                  ⁢                                                                          ⁢                  1                                                      =                          x                              d                ⁢                                                                  ⁢                0                                                                        (        3        )            where x is the displacement value, d0 is the zero displacement value, d1=d0−x is the distance between the plates of capacitor C1, and d2=d0+x is the distance between the plates of capacitor C2. Equation (3) shows that in the ideal case the output voltage V0 of the self-balanced accelerometer is a linear function of the displacement x. Unfortunately, in actual implementations, there are sources of non-linearity not taken into account in Eq. (3).
The two main sources of non-linearity in self-balanced accelerometers are feedthrough capacitance and residual electrostatic force. Feedthrough capacitance (Cft) is any fixed capacitance between the proofmass and the sense electrodes. FIG. 3 illustrates the feedthrough capacitance in a capacitive core 300, an example of which is shown in FIG. 1. The capacitive core 300 includes a first capacitor C1 between a first sense electrode 302 and a proofmass 304, and a second capacitor C2 between a second sense electrode 306 and the proofmass 304. The capacitive core 300 also includes unwanted feedthrough capacitances Cft between the proofmass 304 and each of the sense electrodes 302, 306. Re-deriving Eq. (2) and Eq. (3) taking into account the feedthrough capacitances Cft provides:
                              Vo          ∝                                                    C                1                            -                              C                2                                                                    C                1                            +                              C                2                            +                              2                ⁢                                  C                  ft                                                                    =                                                                              1                  /                  d                                ⁢                                                                  ⁢                1                            -                                                1                  /                  d                                ⁢                                                                  ⁢                2                                                                                      1                  /                  d                                ⁢                                                                  ⁢                1                            +                                                1                  /                  d                                ⁢                                                                  ⁢                2                            +                                                2                  ⁢                                      C                    ft                                                  A                                              =                                                                      d                  ⁢                                                                          ⁢                  2                                -                                  d                  ⁢                                                                          ⁢                  1                                                                              d                  ⁢                                                                          ⁢                  2                                +                                  d                  ⁢                                                                          ⁢                  1                                +                                                                            2                      ⁢                                              C                        ft                                                                                    C                      ⁢                                                                                          ⁢                      0                                                        ⁢                                                                                    ⅆ                        2                                            *                      d                      ⁢                                                                                          ⁢                      1                                                              ⅆ                      0                                                                                            =                          x                                                d                  ⁢                                                                          ⁢                  0                                +                                                                            C                      ft                                                              C                      ⁢                                                                                          ⁢                      0                                                        ⁢                                                            (                                                                        ⅆ                                                      0                            2                                                                          -                                                  x                          2                                                                    )                                                              ⅆ                      0                                                                                                                              (        4        )            which introduces a non-linear term x2 due to the feedthrough capacitance.
Residual electrostatic forces are created on the proofmass when excitation voltages are applied to the sensor to sense the displacement of the proofmass. Single amplifier methods have been tried unsuccessfully to eliminate these residual electrostatic forces. More success has been achieved by adding additional amplifiers to the system to eliminate the residual electrostatic forces. However, these additional amplifiers can take a significant amount of chip area, approximately half of the chip area used for the self-balancing bridge itself. This additional chip area can be expensive.
One method of trying to cancel electrostatic force using a single amplifier is shown in the self-balancing capacitive bridge 400 of FIG. 4. The capacitive bridge 400 includes a capacitive core 402, an amplifier 404, and feedback paths 410, 412. The inverter at the output of the amplifier 404 is not a separate amplifier but simply represents the inverting of the outputs of the amplifier 404. The core 402 produces an output that is amplified by the amplifier 404 to produce an output Vo that is fed back to the inputs of the core 402 where it is combined with a reference voltage Vs. FIG. 5 shows the inputs and outputs of the core 402 during phase φ1 and φ2.
FIG. 5A shows the inputs and outputs of the core 402 during phase φ1. During phase φ1, the output voltage Vo is fed back to the inputs 502, 506 of the capacitors C1 and C2 of the core 402, and the output 504 of the core 402 is connected to ground. Using the relationship that Vo=(x/d0)*Vs, the force on the proofmass during phase φ1 can be expressed as:
                              F                      Φ            1                          =                                                            1                2                            ⁢                                                                    ⅆ                    C                                    ⁢                                                                          ⁢                  1                                                  ⅆ                  x                                            ⁢              V              ⁢                                                          ⁢                              0                2                                      -                                          1                2                            ⁢                                                                    ⅆ                    C                                    ⁢                                                                          ⁢                  2                                                  ⅆ                  x                                            ⁢              V              ⁢                                                          ⁢                              0                2                                              =                                    1              2                        ⁢                                          C                ⁢                                                                  ⁢                0                                            d                ⁢                                                                  ⁢                0                                      ⁢                                          Vs                2                            ⁡                              (                                                                                                    (                                                                              x                            /                            d                                                    ⁢                                                                                                          ⁢                          0                                                )                                            2                                                                                      (                                                  1                          -                                                                                    x                              /                              d                                                        ⁢                                                                                                                  ⁢                            0                                                                          )                                            2                                                        -                                                                                    (                                                                              x                            /                            d                                                    ⁢                                                                                                          ⁢                          0                                                )                                            2                                                                                      (                                                  1                          +                                                                                    x                              /                              d                                                        ⁢                                                                                                                  ⁢                            0                                                                          )                                            2                                                                      )                                                                        (        5        )            
FIG. 5B shows the inputs and outputs of the core 402 during phase φ2. During phase φ2, the positive reference voltage Vs is provided to the input 502 of the capacitor C1, the negative reference voltage −Vs is provided to the input 506 of the capacitor C2, and the output 504 of the core 402 is connected to the amplifier which provides a virtual ground. The force on the proofmass during phase φ2 can be expressed as:
                              F                      Φ            2                          =                                                            1                2                            ⁢                                                                    ⅆ                    C                                    ⁢                                                                          ⁢                  1                                                  ⅆ                  x                                            ⁢              V              ⁢                                                          ⁢                              s                2                                      -                                          1                2                            ⁢                                                                    ⅆ                    C                                    ⁢                                                                          ⁢                  2                                                  ⅆ                  x                                            ⁢              V              ⁢                                                          ⁢                              s                2                                              =                                    1              2                        ⁢                                          C                ⁢                                                                  ⁢                0                                            d                ⁢                                                                  ⁢                0                                      ⁢                                          Vs                2                            ⁡                              (                                                      1                                                                  (                                                  1                          -                                                                                    x                              /                              d                                                        ⁢                                                                                                                  ⁢                            0                                                                          )                                            2                                                        -                                      1                                                                  (                                                  1                          +                                                                                    x                              /                              d                                                        ⁢                                                                                                                  ⁢                            0                                                                          )                                            2                                                                      )                                                                        (        6        )            
The residual electrostatic force on the proofmass can be calculated as the average of the forces on the proofmass during phase φ1 and φ2. Using Eq. (5) and (6), the average force is:
                              F          avg                =                                            (                                                F                                      Φ                    1                                                  +                                  F                                      Φ                    2                                                              )                        /            2                    =                                    1              4                        ⁢                                          C                ⁢                                                                  ⁢                0                                            d                ⁢                                                                  ⁢                0                                      ⁢            V            ⁢                                                  ⁢                                          s                2                            ⁡                              (                                                      1                                                                  (                                                  1                          -                                                                                    x                              /                              d                                                        ⁢                                                                                                                  ⁢                            0                                                                          )                                            2                                                        -                                      1                                                                  (                                                  1                          +                                                                                    x                              /                              d                                                        ⁢                                                                                                                  ⁢                            0                                                                          )                                            2                                                                      )                                      *                          (                              1                +                                                      (                                                                  x                        /                        d                                            ⁢                                                                                          ⁢                      0                                        )                                    2                                            )                                                          (        7        )            This shows that the single amplifier self-balancing capacitive bridge 400 has a non-zero residual electrostatic force.
Another method of electrostatic force cancellation is shown in the self-balancing capacitive bridge 600 of FIG. 6. This method requires the addition of two amplifiers, specifically two summing amplifiers. The capacitive bridge 600 includes a capacitive core 602, a forward amplifier 604, two summing amplifiers 620, 622, and feedback paths 610, 612. The core 602 produces an output that is amplified by the forward amplifier 604 to produce an output Vo that is fed back on feedback paths 610, 612 to the inputs of the core 602. The summing amplifiers 620, 622 are on feedback paths 610, 612, respectively. The first summing amplifier 620 on the first feedback path 610 sums the output signal Vo with a positive reference voltage Vs and outputs Vs−Vo. The second summing amplifier 622 on the second feedback path 612 sums the output signal Vo with the negative reference voltage Vs and outputs −Vs−Vo. FIG. 7 shows the inputs and outputs of the core 602 during phase φ1 and φ2.
FIG. 7A shows the inputs and outputs of the core 602 during phase φ1. During phase φ1, the outputs of the summing amplifiers 620, 622 are coupled to the inputs 702, 706 of the capacitors C1 and C2 of the core 602, and the output 704 of the core 602 is coupled to the amplifier which provides a virtual ground. The force on the proofmass during phase φ1 can be expressed as:
                              F                      Φ            1                          =                                                            1                2                            ⁢                                                                    ⅆ                    C                                    ⁢                                                                          ⁢                  1                                                  ⅆ                  x                                            ⁢                                                (                                      Vs                    -                                          V                      ⁢                                                                                          ⁢                      0                                                        )                                2                                      -                                          1                2                            ⁢                                                                    ⅆ                    C                                    ⁢                                                                          ⁢                  2                                                  ⅆ                  x                                            ⁢                                                (                                      Vs                    +                                          V                      ⁢                                                                                          ⁢                      0                                                        )                                2                                              =                                                    1                2                            ⁢                                                C                  ⁢                                                                          ⁢                  0                                                  d                  ⁢                                                                          ⁢                  0                                            ⁢                                                Vs                  2                                ⁡                                  (                                                                                                              (                                                      1                            -                                                                                          x                                /                                d                                                            ⁢                                                                                                                          ⁢                              0                                                                                )                                                2                                                                                              (                                                      1                            -                                                                                          x                                /                                d                                                            ⁢                                                                                                                          ⁢                              0                                                                                )                                                2                                                              -                                                                                            (                                                      1                            +                                                                                          x                                /                                d                                                            ⁢                                                                                                                          ⁢                              0                                                                                )                                                2                                                                                              (                                                      1                            +                                                                                          x                                /                                d                                                            ⁢                                                                                                                          ⁢                              0                                                                                )                                                2                                                                              )                                                      =            0                                              (        8        )            
FIG. 7B shows the inputs and outputs of the core 602 during phase φ2. During phase φ2, the inputs 702, 706 of both capacitors C1, C2 are coupled to ground and the output 704 of the core 602 is coupled to ground. Since all of the voltages on the core are 0 V during phase φ2, the force on the proofmass Fφ1 is also zero.
The residual electrostatic force on the proofmass can be calculated as the average of the forces on the proofmass during phase φ1 and φ2. Since, as shown above, the force on the proofmass during both phases φ1 and φ2 is zero (0), the average force is also zero (0). Thus, the self-balancing capacitive bridge 600 of FIG. 6 does cancel the electrostatic force, but it requires two additional summing amplifiers 620, 622 to accomplish this cancellation. These two additional summing amplifiers can take up a significant amount of chip space, approximately half the chip area of the capacitive bridge. This additional chip area can be a significant expense.
It would be desirable to reduce or eliminate the nonlinearity due to feedthrough and parasitic capacitances, and it would also be desirable to reduce or eliminate the nonlinearity due to residual electrostatic forces using less additional circuitry without requiring significant additional chip area, such as by the summing amplifiers of the embodiment 600. Reducing or eliminating either or both of these unwanted effects would reduce primary sources of non-linearity in self-balanced capacitive bridges.